1. Field of the Invention
The present invention relates to an output interface circuit and more particularly, to an output interface circuit to be placed between an internal circuit or circuits and an external terminal, which is used as an interface circuit for/in outputting an output signal of the internal circuit or circuits to the external output terminal.
2. Description of the Related Art
In recent years, the need to increase the integration scale of electronic elements/components on a semiconductor integrated circuit device (which is referred as a xe2x80x9cLSIxe2x80x9d hereinafter) and to reduce the power consumption thereof has become stronger. To meet the need, various techniques have been developed to lower the supply voltage for a LSI from popular 5 V to a lower one such as 3.3 V or 2 V.
A LSI is usually built into an external device or apparatus and therefore, a LSI is supplied with its supply voltage from the external device/apparatus. In this case, the LSI is supplied with a conventional supply voltage of 5 V or a recent one of 3.3 V or 2 V. This means that the value of the supply voltage for a LSI varies dependent on what value of voltage an external device/apparatus supplies to a LSI incorporated. Taking this fact into consideration, a proper contrivance needs to be provided in such a way that a LSI operates normally not only at a higher supply voltage of 5 V but also at a lower one of 3.3 V or 2 V.
Recently, when the designed supply voltage of a LSI is 3.3 or 2 V, a voltage-lowering circuit has been often provided in the power supply circuit of a LSI to lower the incoming supply voltage of 5 V to 3.3 or 2 V. In this case, a desired supply voltage of 3.3 or 2 V is produced by the voltage-lowering circuit built in the LSI and then, it is supplied to the internal circuit(s) thereof.
In this specification, a supply voltage (e.g., 3.3 or 2 V) generated and supplied inside a LSI itself is termed an xe2x80x9cinternal supply voltagexe2x80x9d while a supply voltage (e.g., 5 V) supplied from an external device/apparatus located outside the LSI is termed an xe2x80x9cexternal supply voltagexe2x80x9d. Moreover, a circuit for generating an xe2x80x9cinternal supply voltagexe2x80x9d inside a LSI is termed an xe2x80x9cinternal power supply circuitxe2x80x9d while a circuit for generating an xe2x80x9cexternal supply voltagexe2x80x9d in an external device/apparatus located outside the LSI is termed an xe2x80x9cexternal power supply circuitxe2x80x9d.
Some prior-art output interface circuits of this type are capable of normal operation at both an internal supply voltage of 3.3 V or 2 V and an external supply voltage of 5 V. These circuits are termed xe2x80x9cvoltage tolerant circuitsxe2x80x9d, an example of which is shown in FIG. 1.
In FIG. 1, a prior-art LSI 200 is incorporated into a specific external device or apparatus (not shown). Only an external power supply circuit 69 of the external device is shown in FIG. 1 for simplification of illustration.
Practically, the prior-art LSI 200 comprises various internal circuits to realize its specific functions. However, only one of the internal circuits is shown in FIG. 1 with the reference numeral 61 for simplification. Although the LSI 200 comprises practically various external terminals for outputting its output signals, only one of them is shown in FIG. 1 with the reference numeral 67. The terminal 67 is used to derive an output signal S61 of the internal circuit 61 (i.e., the LSI 200). The LSI 200 further comprises a prior-art output interface circuit 62 and an internal power supply circuit 68.
The output interface circuit 62 provides a specific interface function between the internal circuit 61 and the external output terminal 67. The internal power supply circuit 68 supplies a specific internal supply voltage VINT (=3.3 V) to the inside of the LSI 200 including the internal circuit 61 and the output interface circuit 62.
The external power supply circuit 69, which is incorporated into the external device, is located outside the LSI 200. The circuit 69 supplies a specific external supply voltage VINT (=5 V or 3.3 V) to the inside of the LSI 200 including the output interface
The output interface circuit 62 comprises a 5V-system output buffer circuit 63 that provides its optimum operation at a supply voltage of 5 V and a 3.3V-system output buffer circuit 64 that provides its optimum operation at a supply voltage of 3.3 V. These two buffer circuits 63 and 64 are alternately activated or used dependent on the current value (5 V or 3.3 V) of the external supply voltage VEXT supplied by the external power supply circuit 69.
The internal circuit 61 is supplied with the internal supply voltage VINT (3.3 V) from the internal power supply circuit 68. The 5V-system output buffer circuit 63 is supplied with the external supply voltage VEXT (5 V or 3.3 V) from the external power supply circuit 69 and the internal supply voltage VINT (3.3 V) from the internal power supply circuit 68. The 3.3V-system output buffer circuit 64 is supplied with the external supply voltage VEXT (5 V or 3.3 V) or the internal supply voltage VINT (3.3 V) by way of a switch 65.
The output signal S61 of the internal circuit 61 is applied to both the 5-system output buffer circuit 63 and the 3.3V-system output buffer circuit 64. In response to the signal S61, the 5V-and 3.3V-system output buffer circuits 63 and 64 output their output signals S63 and S64, respectively. One of the signals S63 and S64 is sent to the external output terminal 67 by way of a switch 66.
Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETS) that constitute the 5V-system output buffer circuit 63 are different in characteristics from those that constitute the 3.3V-system output buffer circuit 64. Specifically, the maximum supply voltage applied to the circuit 63 is greater than that applied to the circuit 64. Thus, the gate insulator thickness of the MOSFETs of the circuit 63 is larger than that of the circuit 64 and at the same time, the logic threshold of the MOSFETs of the circuit 63 is higher than that of the circuit 64.
Due to the characteristic difference, when the external supply voltage VEXT is 5 V, the switch 66 is controlled to interconnect the 5V-system output buffer circuit 63 to the external output terminal 67 and at the same time, the switch 65 is controlled to interconnect the 3.3V-system output buffer circuit 64 to the internal power supply circuit 68. As a result, the output signal S63 of the circuit 63 operable at the external supply voltage VEXT of 5 V is derived from the output terminal 67. The output signal S64 of the circuit 64 operable at the internal supply voltage VINT of 3.3 V is not sent to the output terminal 67.
When the external supply voltage VEXT is 3.3 V, the switch 66 is controlled to interconnect the 3.3V-system output buffer circuit 64 to the external output terminal 67 and at the same time, the switch 65 is controlled to interconnect the 3.3V-system output buffer circuit 64 to the external power supply circuit 69. As a result, the output signal S64 of the circuit 64 operable at the external supply voltage VEXT of 3.3 V is derived from the output terminal 67. The output signal S63 of the circuit 63 is not sent to the output terminal 67. This is because the external supply voltage VEXT of 3.3 V is supplied to the circuit 63 and thus, the signal S63 has undesired characteristics.
As explained above, with the prior-art LSI 200 of FIG. 1, when the external supply voltage VEXT is 5 V, the output signal S63 of the 5V-system buffer circuit 63 operable optimally at 5 V is derived from the output terminal 67. When the external supply voltage VEXT is 3.3 V, the out put signal S64 of the 3.3V-systembuffer circuit 64 operable optimally at 3.3 V is derived from the output terminal 67. Thus, an optimum interface operation is provided independent of whether the external supply voltage VEXT is 5 V or 3.3 V.
The switches 65 and 66 are usually formed with wiring lines made of conductive material such as aluminum (Al), not with the use of transistors. In detail, the switches 65 and 66 are usually realized by changing the interconnection of the wiring lines (i.e., changing the mask patterns for the wiring lines) dependent on the value (i.e., 5 V or 3.3 V) of the external supply voltage VEXT.
With the prior-art output interface circuit 62 described above with reference to FIG. 1, there are two problems described below.
First, when the external supply voltage VEXT is 5 V, the 5V-system output buffer circuit 63 is connected to external output terminal 67 by way of the switch 66. Thus, the circuit 63 provides its interface operation even if the voltage VEXT varies between 5 V and 3.3 V or between 5 V and 2 V. On the other hand, as explained above, the gate insulator thickness of the MOSFETs of the 5V-system circuit 63 is larger than that of the 3.3V-system circuit 64 and the logic threshold of the MOSFETs of the circuit 63 is higher than that of the circuit 64. Therefore, if the voltage VEXT is lowered to near 3.3 V or 2 V, the delay time of the output signal S63 of the circuit 63 tends to increase abruptly, resulting in incapability of a desired fast and stable interface operation.
For example, when the prior-art LSI 200 is driven by a battery, the external supply voltage VEXT is inclined to fluctuate between 5 V and 3.3 V or between 5 V and 2 V. This is because the designed output voltage (=5 V) of a battery usually fluctuates dependent on the total time of use and/or the loaded condition, and because the output voltage tends to lower gradually from 5 V during the operation of the LSI 200 due to discharge.
Second, the switching operation between the 5V- and 3.3V-system output buffer circuits 63 and 64 is realized by changing the interconnection (i.e., the mask pattern) of the wiring lines dependent on a required value (i.e., 5 V or 3.3r V) of the external supply voltage VEXT. Therefore, these circuits 63 and 64 are unable to be switched in response to the value change of the voltage VEXT after the interconnection is once determined.
If the switches 65 and 66 are formed with the use of transistors, the second problem can be solved. In this case, however, the size of the transistors will be excessively large in order to keep the desired buffering characteristics of the circuits 63 and 64. In other words, the total chip area of the switches 65 and 66 will be equal to or greater than that of the circuits 63 and 64 themselves. Thus, there arises another problem of chip-size increase of the LSI 200.
Accordingly, an object of the present invention is to provide an output interface circuit that realizes a desired fast and stable interface operation without any chip-size increase even if the external supply voltage varies within a specific range (e.g., from 5 V to 3.3 or from 5 V to 2 V).
Another object of the present invention is to provide an output interface circuit that prevents a voltage exceeding the current external supply voltage from being applied to the external output terminal when the external supply voltage is lower than the internal supply voltage.
Still another object of the present invention is to provide n output interface circuit that prevents a voltage exceeding the internal supply voltage from being applied to a buffer circuit for a lower voltage (e.g., 3.3 V) when a buffer circuit for a higher voltage (e.g., 5 V) is used or activated.
The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description.
An output interface circuit according to the present invention comprises:
(a) a first output buffer circuit for receiving an output signal of an internal circuit to output a first output signal;
(b) a second output buffer circuit for receiving the output signal of the internal circuit to output a second output signal; and
(c) an output-level adjusting circuit for receiving the second output signal outputted from the second output buffer circuit and for adjusting a level of the second output signal thus received to output a third output signal corresponding to the level-adjusted second output signal to an external output terminal;
wherein the first output buffer circuit outputs the first output signal to the external output terminal responsive to a first control signal that represents an external supply voltage having a first relationship with a specific value; and
wherein the second output buffer circuit outputs the second output signal to the output-level adjusting circuit responsive to a second control signal that represents the external supply voltage having a second relationship with the specific value opposite to the first relationship.
With the output interface circuit according to the present invention, (a) the first output buffer circuit for receiving the output signal of the internal circuit to output the first output signal; (b) the second output buffer circuit for receiving the output signal of the internal circuit to output the second output signal; and (c) the output-level adjusting circuit for receiving the second output signal outputted from the second output buffer circuit and for adjusting the level of the second output signal thus received to output the third output signal corresponding to the level-adjusted second output signal to the external output terminal are provided.
Moreover, the first output buffer circuit outputs the first output signal to the external output terminal responsive to the first control signal that represents the external supply voltage having the first relationship with the specific value. The second output buffer circuit outputs the second output signal to the output-level adjusting circuit responsive to the second control signal that represents the external supply voltage having the second relationship with the specific value opposite to the first relationship.
Therefore, when the external supply voltage has the first relationship with the specific value, the first output buffer circuit outputs the first output signal to the external output terminal responsive to the first control signal. On the other hand, when the external supply voltage has the second relationship with the specific value opposite to the first relationship, the second output buffer circuit outputs the second output signal to the output-level adjusting circuit responsive to the second control signal. Then, the output-level adjusting circuit outputs the third output signal to the external output terminal.
As a result, for example, if the external supply voltage is higher than the specific value, the first output signal, which corresponds to the output signal of the internal circuit, is outputted to the external output terminal by the first output buffer circuit. If the external supply voltage is not higher than the specific value, the second output signal, which corresponds to the output signal of the internal circuit, is outputted to the external output terminal by the second output buffer circuit. Thereafter, the third output signal corresponding to the level-adjusted second output signal is outputted to the external output terminal by the output-level adjusting circuit. Accordingly, even if the external supply voltage varies within a specific range (e.g., from 5 V to 3.3or from 5V to 2 V), a desired fast and stable interface operation is realized.
Moreover, which one of the first and second output signals is used dependent on the first or second relationship of the external supply voltage is controlled with the first and second control signals. Thus, there is no need to provide a transistor switch for switching from the first output signal to the second one and vice versa. This means that chip-size increase is prevented.
In a preferred embodiment of the circuit according to the invention, the output-level adjusting circuit has a function of equalizing a voltage level of the third output signal to the external supply voltage when the external supply voltage is lower than an internal supply voltage. In this embodiment, there is an additional advantage that a voltage higher than the external supply voltage is prevented from being outputted to the external output terminal when the external supply voltage is lower than the internal supply voltage.
In another preferred embodiment of the circuit according to the invention, the output-level adjusting circuit has a function of adjusting a voltage level of the third output signal to be lower than an internal supply voltage. In this embodiment, there is an additional advantage that a voltage higher than the internal supply voltage is prevented from being applied to the second output buffer circuit when the first output buffer circuit is used.
In still another preferred embodiment of the circuit according to the invention, the first output signal outputted from the first output buffer circuit is approximately equal to the external supply voltage while the second output signal outputted from the second output buffer circuit is approximately equal to an internal supply voltage. In this embodiment, it is preferred that the third output voltage outputted from the output-level adjusting circuit is approximately equal to the external supply voltage.
In a further preferred embodiment of the circuit according to the invention, the first and second control signals are respectively sent to the first and second output buffer circuits by way of a register that stores a data on a current state of the external supply voltage.
In a still further preferred embodiment of the circuit according to the invention, the first and second control signals are respectively sent to the first and second output buffer circuits by way of a voltage detection circuit for continuously detecting a state of the external supply voltage.